general description the GD90590 evaluation board is de - signed for testing the performance of the high-speed integrated device gd16590, a high-speed clock synthesizer with pll. the gd16590 generates six differential high-speed clocks from a common on- chip vco or an external vcxo. the on-chip integrated pll locks the outputs to one of three selectable input reference clocks. all outputs are dc terminated on the evaluation board. during the board design special attention has been paid to optimise the overall per - formance, with consideration of the gd16590?s linear characteristics. de-coupling capacitors are located as close as possible to the device, and the signal carrying traces in the pcb are kept free from via holes, sharp corners etc. to make the transmission line design as smooth as practically possible. an intel company data sheet rev.: 04 preliminary features easy evaluation of high-speed perfor - mance in carefully designed pcb. high-speed data in/outputs available via standard sma connectors. integrated 50 transmission lines in the pcb ensure matching intercon - nection of input and output signals. input and output signals are ac coupled, i.e. the device can be used with circuits with positive as well as negative supply. single unregulated power supply: +6 v, 400 ma. board dimensions: 101 133 mm incl. connectors. gerber files for pcb layout available on request. high-speed clock synthesizer evaluation board GD90590
functional details general the gd16590 offers a fully integrated pll including on-chip vco, and with inputs for use of an external vcxo. three selectable differential reference clock inputs and six subdivided differential oscillator outputs are available on the GD90590 evaluation board. reference clock inputs the three differential reference clock inputs (j3/j4, j5/j6 and j7/j8) are ac coupled lvpecl inputs, internally terminated in the gd16590 device. selection of the active input is done from dip switch (s1). clock output signals the subdivided clock outputs are generated as differential lvpecl signals. each signal is dc terminated on the board via 120 to ground. the signals are ac coupled out of the board to the sma connectors (j10?j21). the signals can be dc cou - pled to the load if the internal termination resistors are removed and the coupling capacitors are replaced by 0 resistors. each of the six outputs can be switched off by pulling the correspond - ing lvt select signal (outenax) to ground. the output select signals are controlled by dip switch (s2). important note : failure to terminate an active (enabled) output may cause degradation of the device performance. loop filter the pll loop filter is composed of the components r49/c24. for a specific application the mounted default values may need to be changed for optimum performance since the jitter perfor- mance of the pll depends on the input frequency. there is space for an additional loop filter capacitor (c25). when the in- ternal vco is used, the loop current flows from ochp via r46 to the vctl input. on-board vcxo the GD90590 evaluation board comprises a vcxo mounted in position u4. this vcxo may be used as an alternative to the vco integrated in the gd16590. when the vcxo is used the control loop for the pll comprises an active loop filter com - posed of the operations amplifier (u3 - lmv358m). the filter, which has a dc adjustment of the working point in p3, controls the vcxo (u4 - vf900409). the vcxo output is ac coupled via c45 to the vcxo input terminal of the gd16590. the vcxo input is a differential input to the gd16590. hence the trigger point of the device, i.e. the input duty cycle can be adjusted by p1. external oscillator an alternative to the on-chip vco and the on-board vcxo is to add an external clock signal. use j1 (vcxo) for single ended input or j1/j2 (vcxo/dccal) for differential input. the external clock is terminated in r13/r18. remove capacitors c40 and c45 to avoid stub reflections and conflicts with u4. when using single ended input duty cycle can be adjusted by means of p1, if r5 = 470 is mounted. mode control the gd16590 compares selected reference clock input signal with the selected subdivided oscillator frequency. the charge pump output ochp reflects the phase relationship between the compared signals. the frequency of the charge pump output (the error signal frequency) follows the reference clock fre - quency directly. this means the gain of the pll loop is directly proportional with the input reference clock frequency. hence you should expect the jitter performance of the application to be dependent on the reference clock frequency in use. general purpose clock divider operation in addition to the frequency limited clean-up operation the gd16590 can be used as a general purpose high speed clock divider. the clock input is j1(/j2) as described above, and one or more outputs will provide a binary divided clock output in the terminals j10?j21, depending on the output enable signal set - ting in dip switch (s2). power supply the GD90590 evaluation board may be powered from an un - regulated power supply, delivering +6 v, 400 ma minimum. a stabilised 3.3 v supply for the gd16590 is generated locally on the board. data sheet rev.: 04 GD90590 page 2 of 5
data sheet rev.: 04 GD90590 page 3 of 5
dip switch factory settings s1 ? divisor select, clock input select. on=0,off=1 s1-1 on sel1 control select input reference source. s1-2 on sel2 control s1-3 off sel3 control select clock frequency for phase detector input. s1-4 on sel4 control s1-5 on sel5 control s1-6 on vcosel1 control select clock source for the divider. s1-7 off vcosel2 control please refer to gd16590 data sheet for description. s2 - output enable selection on=0= output disable, of f=1= output enable s2-1 off output fouta s2-2 off output foutb s2-3 on subdivided output fout2 s2-4 on subdivided output fout4 s2-5 on subdivided output fout8 s2-6 on subdivided output fout16 references gd16590 data sheet (latest revision). gd16590 test report, available from giga a/s. data sheet rev.: 04 GD90590 page 4 of 5
ordering information to order, please specify as shown below: order number: description: GD90590 the evaluation kit comprises: evaluation board in antistatic bag gd16590 device mounted on the board how to get started GD90590 data sheet (this document) GD90590, data sheet rev.: 04 - date: 20 december 2000 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.giga.dk please check our internet web site for latest version of this data sheet. distributor: copyright ? 2000 giga a/s all rights reserved an intel company
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